The present invention relates to integrated memory circuit, and in particular, to so-called NROM memories that are based on a dielectric layer for storing information.
In the technical publication xe2x80x9cCan NROM, two-bit, trapping storage NVM cell, give a real challenge to floating gate cells?xe2x80x9d, B. Eitan et al., International Conference on Solid State Devices and Materials, Tokyo, 1999, discloses a memory circuit having an array of NROM memory cells. The NROM concept is a two bit Flash cell based on charge storage in an ONO dielectric. ONO stands for oxide-nitride-oxide. One memory cell is storing two physically separated bits with a unique method to sense the trapped charge. Programming is performed by Channel Hot Electron injection (CHE) and erase is performed by tunnelling enhanced Hot Hole Injection.
Gene rally, a NROM cell is a n-channel MOSFET device where the gate dielectric is replaced by a trapping material (nitride) sandwiched between two silicon dioxide layers. This is the above mentioned ONO structure. The top and bottom oxides are thicker than 1,5 nanometers to avoid any direct tunneling. The charge is stored in nitride next to the n+ junctions. Each NROM cell includes a source region, a drain region and a channel region extending between the source and the drain region.
In this prior art memory cell, the drain regions on the one hand and the source regions on the other hand of neighboring memory cells are connected by so-called bit lines that are highly doped regions within the substrate semiconductor material. Generally, a p doped semiconductor substrate is used. The bit lines are realized as heavily doped n regions. Above the heavily doped n regions, an oxide for insulation purposesxe2x80x94the bit line oxidexe2x80x94is provided. This kind of bit lines are called xe2x80x9cburiedxe2x80x9d bit lines.
Above the channel region, the ONO structure is applied. Above the ONO structure, the xe2x80x9cgate electrodexe2x80x9d that is also called word line is provided. In particular, word lines are provided such that they cross the bit lines at angles of approximately 90xc2x0. Such an area of memory cells being comprised of an array of parallel bit lines and an array of parallel word lines being formed above the bit lines and crossing the bit lines at 90xc2x0 angles is called a virtual ground array. Usually, this virtual ground array is a field-oxide-less cross point architecture with a 5-6 F2 cell size or 2.5-3 F2 per bit.
The NROM cell is programmed by channel hot electron injection. At a high gate potential the transistor is driven into pinch off, if a sufficient source to drain voltage is applied. Electrons are heating up at high fields near the drain junction. As soon as the electrons have reached a certain velocity, they are injected into the nitride layer of the ONO structure because of the corresponding voltage applied to the word line, i.e., the gate of the NROM memory cell.
This electron injection into the nitride layer takes place near the metallurgical junction of the drain region to which the electrons move. Since the electrons can not freely move within the nitride layer, the electrons are trapped approximately at the edge of a crossing region of a word line and a bit line.
When the drain source voltage is reversed, electrons are accelerated in the reverse direction. When these electrons have reached a certain velocity, they are injected into the nitride layer near the crossing region of the word line and the other bit line of the memory cell. Since the electrons are not freely movable within the nitride layer of the ONO structure, one memory cell can store two bits. The storing locations are the edges of the crossing point of the word line and the first bit line of a memory cell, and the edges of the other crossing point of the word line and the other bit line of the memory cell.
Generally, it is a design aim to minimize the size of a memory cell. When the cell size can be reduced, the memory circuit having a certain storage capacity can be made smaller. The other way round, a memory circuit having the same size has a higher storage capacity, when a memory cell is made smaller.
A former limitation to memory cell minimization was the fact that a certain channel length is required for the device. The barrier heights of the layer materials are around 3.1 eV which requires the electrons to be heated up enough to surpass this barrier during programming. A typical drain voltage is, therefore, 5 V. To avoid punch through the effective channel length can not be reduced as much as desired.
To minimize the cell size while maintaining a certain required channel length, the U.S. patent application publication U.S. Ser. No. 2002/0024092 A1 teaches to use a grooved channel region. The channel shape is changed from a straight channel shape to a kind of a two dimensional channel shape, since the active channel is not formed by a straight connection but by U shape or V shape at the bottom of a channel groove. The ONO structure is applied onto the surface of the channel groove. With this groove shape, the memory cell size can be reduced in order to accommodate a higher capacity memory on a certain chip size.
The memory cell in the above identified US patent application publication has diffused bit lines, i.e., bit lines, that are produced by heavily doping certain regions of the semiconductor substrate.
It is well known that instead of heavily doping, these bit lines still have a certain ohmic resistance that is much higher than the ohmic resistance of a metallic layer for example. On the other side, relatively high voltages have to be applied to the drain or source region. The voltages lie in the range of 4.5 volts. To reduce ohmic losses in the bit lines, the so-called bit line strapping technique is used. With this technique, via holes are applied between adjacent word lines. These via holes extend between a top metal or metallized layer and the bit line, i.e., the diffused regions that are heavily doped. With this arrangement, the ohmic resistance of the bit lines is not mainly determined by the heavily doped diffused regions but is determined by the ohmic resistances of the metal or metallized layer and the contact via holes.
A disadvantage of this concept is that it becomes increasingly difficult to produce these via holes between adjacent word lines, since the patterning of the word lines is to be conducted by photolithography. Additionally, the word line photolithography is a very demanding task, since the structures are in the range of 150 to 50 nanometers. One can imagine that it is very difficult to apply a via hole which itself has a diameter of possibly 50 nanometers in a space of only 100 nanometers or less. Due to the relatively high maximum voltage (about 10 V) between bit lines and word lines a sufficient insulation layer thickness is required if reliability problems are to be avoided. In addition, the word line to bit line capacity should be kept low to avoid switching delay.
To address this problem, we have proposed in our commonly assigned, copending application Ser. No. 09/600,649, filed Jul. 6, 2001, to not use the bit line strapping technique but to apply a bit line structure having several layers onto the semiconductor substrate. Bit lines are formed of a polysilicon layer directly applied to the substrate semiconductor surface. On this polysilicon layer a metal containing layer is applied. This metal containing layer is, e.g. tungsten silicide and, additionally, a hard mask layer, e.g. an oxide, for electric insulation of the tungsten silicide layer from the respective environment. Thus, this bit line applied on top of the substrate is formed of a polysilicon layer, a tungsten silicide layer and a top oxide layer. Instead of WSi, also tungsten nitride and tungsten can be applied. Additionally, titan and/or titan silicide can be used.
It has been discovered that, though the problems involved with bit line strapping are overcome by this solution, another problem has appeared. It has been outlined above, that the word line lithography is a very demanding task. In particular, the quality of the lithography heavily deteriorates, when the surface, on which the lithography is conducted, is not a perfect surface but has steps or, generally, different levels.
Normally, an integrated memory circuit includes an array of memory cells located within a periphery. On this periphery, a controlling circuit for controlling the array of memory cells is located. It is clear that the bit lines as well as the word lines of the array of memory cells extend into the controlling circuit on the periphery so that the required voltages can be applied to the word lines as well as the bit lines.
While the manufacturing steps for forming for example the gate grooves are restricted to the memory cell array, at least the photolithography for producing the word line xe2x80x9ctouchesxe2x80x9d the memory cell array as well as the controlling circuit on the periphery. In particular the photolithography step for forming the word line is also used for defining gate structures of field effect transistors in transistor circuits of the controlling circuit that is normally based on CMOS techniques.
Applying the bit lines onto the substrate semiconductor surface inevitably results in a step between the controlling circuit of the integrated memory circuit and the array of memory cells. In particular, the mask for defining the word lines in the memory cell array is not perfectly plain but has a step at the border between the periphery and the memory cell array.
This step results in problems that lead to a lower yield or forbids further gains in size reduction of the memory cells. In both scenarios, the cost for a memory circuit increase. When the production yield is reduced, the price for a functioning memory circuit has to be raised. When, on the other hand, further gains in size reduction are not possible, the price of the memory cells also is increased because of higher area consumption of a memory cell having a certain capacity.
It is to be pointed out here that the memory circuit market is a very competitive market, in which small price differences may be responsible for the survival of the memory circuit producer.
It is an object of the present invention to provide a cheaper integrated memory circuit or a method of producing a cheaper integrated memory cell.
In accordance with the present invention, this object is achieved by an integrated memory circuit, comprising: a semiconductor substrate having a semiconductor substrate surface plain; an array of memory cells formed on the substrate, the array of memory cells including bit lines and word lines, the bit lines and word lines connecting the memory cells, the bit lines being formed of a material different from a material of the substrate and having a bit line top plane; a controlling circuit formed on the substrate for controlling the array of memory cells, wherein the bit lines and the word lines extend into the controlling circuit, wherein the bit lines are recessed with respect to the semiconductor substrate surface plane such that a difference between the bit line top plane and the semiconductor substrate surface plane is smaller than a predetermined value.
In accordance with a second aspect of the present invention, this object is achieved by a method of forming an integrated memory circuit, the method comprising: providing a semiconductor substrate; forming bit line recesses in the substrate; forming bit lines in the recesses, wherein two adjacent bit lines are connected to a source and a drain region of a memory cell in an array of memory cells; forming gate regions of the memory cells; forming word lines on the gate regions of the memory cells and gate structures of transistors in a control circuit for the array of memory cells, the word lines and the bit lines extending into the control circuit.
The present invention is based on the finding that for further gains in size reduction, it is of utmost importance that before any photolithography steps of highest resolution are carried out, the surface of the substrate has to be as even as possible. In particular, this situation exists for the photolithography for defining the word lines. To achieve a surface or plane of the substrate that is perfectly even or has only negligible steps, i.e., steps that are smaller than a predetermined value which is dictated by the photolithography settings, the bit lines of the inventive integrated memory circuit are recessed with respect to a substrate semiconductor surface plane of the periphery, in which the controlling circuit is produced. By forming recesses into the semiconductor substrate, and, then by forming bit lines in these recesses, a perfect or almost perfect surface for the word line lithography can be obtained. In particular, providing recesses for the bit line allows to form bit lines of a material different from the semiconductor substrate, i.e. bit lines that are preferably metallized or include a metal/semiconductor compound that has a low ohmic resistance. Therefore, the problematic bit line strapping technique can be avoided.
It is an advantage of the inventive concept that by providing recesses for the bit lines, it is possible to obey the essential rules for device functionality and manufacturability in a leading edge fabrication site that is capable of line widths of around 100 nanometers.
It is a further advantage of the present invention that by providing recessed bit lines, no steps of more than about 100 nanometers, preferably 50 nanometers and most preferably 30 nanometers are present, before a critically, i.e., minimum line width lithography like that of the word lines is applied.
It is a another advantage of the present invention that a channel length of around 200 nanometers is possible though the bit line pitch should be scaleable with a cell size of less than 5 F2. It is another advantage of the present invention that a virtual ground NOR array with metallized bit lines can be produced in order to avoid bit line strapping which would require extra space between word lines for contact holes.
It is another advantage of the present invention that the channel length that is defined by both n+ implant depth and the active trench etch process is manufacturable with minimum process and uniformity variation, i.e., with high reproducibility. This is made possible by the fact that the two process steps, i.e., the implant step for forming the source and drain regions and the active channel etch step are related to the same original surface.
It is another advantage of the present invention that an insulation between neighboring channels can be easily integrated utilizing the well-known shallow trench insulation technique. Such shallow trench insulation between neighboring word lines reduces cross talk between adjacent memory cells, which would reduce the performance of the memory cells because of increasing fields that are accompanied by reduced word line spacing.
While currently NROM cells are fabricated as planar type NMOS transistors using an ONO stack dielectric as gate dielectric, the inventive concept allows to use the grooved channel technique together with metallized bit lines. Nitride in this case is used as an electron storage layer. Due to material specific properties, source-drain voltages of 4 to 6 V are necessary during program and erase operations. The transistor channel lengths can thus not be scaled with the decreasing design rule available in modern semiconductor fabrication sites, but are bound to around 200 nanometers. Using grooved channel regions together with recessed bit lines that are, in addition, made by metal or metal compound layers, in combination with shallow trench insulation will result in further memory size reductions that are mainly made possible by the recessed bit lines and, as a consequence, a perfect surface for the final word line lithography.